Capture clock generator using master and slave delay locked loops

ABSTRACT

A clock generator comprises a master delay locked loop (DLL) and a slave DLL to capture a data signal. The slave DLL generates a slave output signal based on a clock signal. The master DLL receives the slave output signal and compensates variations in delays of the data and clock signals to generate a capture clock signal. When the master and slave DLLs are locked, the capture clock signal is center aligned with the data signal.

This application is a Continuation of U.S. application Ser. No.09/838,525, filed Apr. 19, 2001 which is incorporated herein byreference.

TECHNICAL FIELD OF THE INVENTION

The present invention relates generally to data communication, and inparticular to a capture clock generator.

BACKGROUND OF THE INVENTION

In data communication, data are often transferred from one circuit toanother circuit for processing. To capture a data signal, a data capturecircuit is used. The data capture circuit normally uses a clock signalto capture the data signal. The clock signal can be a system clocksignal or an internal clock signal generated by a clock generator.

FIG. 1A is a block diagram illustrating one traditional clock and datasignal relationship of a capture circuit. In this method, the systemclock signal is edge aligned with the captured data signal while thecapture clock signal is center aligned with the data eye. In otherterms, the capture clock signal is 90 degrees out of phase or one-fourthclock cycle delayed from the system clock signal and is center alignedwith the data signal.

FIG. 1B illustrates possible data and clock paths of a capture circuitin a memory device or a memory controller. In this circuit, a data latch(DQ latch) uses a capture clock signal (CAPCLK) to capture an internaldata signal (Din). The Din signal is a delayed version of an externaldata signal (DQ), which travels on a data path including a data pad (DQpad) and a data receiver and driver (D Rx). The data path has a delayindicated by dly-DQ. The CAPCLK is provided by a clock distribution treeas a delayed version of an output clock signal (CLKout). The clockdistribution tree has a delay indicated by dly-CLK. The CLKout clocksignal is generated by a clock generator based on a system clock or anexternal clock signal (XCLK). The XCLK signal is edge aligned with theDQ signal.

From the data and clock paths of FIG. 1B, even if the CLKout signal is90 degrees out of phase with the XCLK signal, the capture clock signal,CAPCLK, may not be center aligned with the Din data signal because ofvariations in delays of the dly-DQ and dly-CLK.

Conventionally, different techniques are used to match the delays of thedata and clock paths, such as the dly-DQ and dly-CLK, to center alignthe capture clock signal to the data signal. A common characteristic ofthese techniques is adding delay elements to the data or clock path orboth. The delay elements are then manually tuned in as an attempt tocompensate the variations in delays between the clock and data paths. Insome cases, tuning the delay elements may not provide satisfactory levelof accuracy. Thus, the clock and data signals may not accurately bealigned for some devices, especially for high speed devices such as newgenerations of memory devices.

There is a need for another technique to generate a capture clock signalthat is accurately center aligned with the data signal.

SUMMARY OF THE INVENTION

The present invention includes a novel capture clock generator havingmaster and slave delay locked loops (DLLs) to generate a capture clocksignal to capture a data signal. When the DLLs are locked, the captureclock signal is center aligned with the data signal.

In one aspect, a capture clock generator includes a receiving circuit toreceive an external clock signal to produce an internal clock signal. Adata receiver receives an external data signal to produce an internaldata signal. A first DLL receives the internal clock signal to producean output clock signal. The output clock signal is 90 degrees out ofphase with the internal clock signal. A second DLL selectively connectsto the first DLL to receive the output clock signal to generate acapture clock signal. When the second DLL is locked, the capture clocksignal is 90 degrees out of phase with the internal data signal.

In another aspect, a method of generating a data signal includesreceiving an external clock signal to generate an internal clock signal.An output clock signal is generated based on the internal clock signal.The output clock signal is 90 degrees out of phase with the internalclock signal. A capture clock signal is generated based on the outputclock signal. The capture signal is used to captured an internal datasignal to produce an output data signal. The output data signal iscenter aligned with the external clock signal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a diagram showing timing relationship between clock and datasignals of a prior art capture circuit in FIG. 1B.

FIG. 1B is a block diagram of a prior art capture circuit.

FIG. 2 is a block diagram of a clock generator according to oneembodiment of the invention.

FIG. 3 is a timing diagram of the operation of the clock generator ofFIG. 2.

FIG. 4 is a diagram showing details of timing delays of the clockgenerator of FIG. 2.

FIG. 5 is a block diagram of a slave DLL of the clock generator of FIG.2.

FIG. 6 is a timing diagram of the slave DLL of FIG. 5.

FIG. 7 is a block diagram of a clock generator according to anotherembodiment of the invention.

FIG. 8 is a block diagram of a memory device having the clock generatoraccording to one embodiment the invention.

FIG. 9 is a block diagram of a system according to one embodiment of theinvention.

DETAILED DESCRIPTION OF THE INVENTION

The following detailed description refers to the accompanying drawingswhich form a part hereof, and in which is shown, by way of illustrationspecific embodiments in which the invention may be practiced. Theseembodiments are described in sufficient detail to enable those skilledin the art to practice the invention, and it is to be understood thatother embodiments may be utilized and that logical, mechanical andelectrical changes may be made without departing from the spirit andscope of the present invention. The following detailed description is,therefore, not to be taken in a limiting sense, and the scope of theinvention is defined only by the appended claims.

FIG. 2 is a block diagram of a clock generator 100 according to oneembodiment of the invention. Clock generator 100 includes a receivingcircuit 102, which has a clock receiver 103 (C Rx) connected to a datareceiver model 105. Receiving circuit 102 receives an external clocksignal XCLK at node 104 and provides an internal clock signal CLKIN atnode 106. A data receiver 122 (D Rx) receives an external data signal DQat node 124 and provides an internal data signal Din at node 126. Thedata receiver model 105 is used to track the delay of data receiver 122.Data receiver 122 and data receiver model 105 are identical.

A slave DLL 114 connects to receiving circuit 102 at node 106 to receivethe CLKIN signal and generate a slave output clock signal CLK90. TheCLK90 is 90 degrees out of phase with the CLKIN signal when slave DLL114 is locked.

A digital master DLL 112 connects to receiving circuit 102 and slave DLL114 through a multiplexor (MUX) 116. Based on the selection of MUX 116,master DLL 112 receives either the CLKIN or the CLK90 signal to generatea capture clock signal CAPCLK. The CAPCLK is used to capture the Dinsignal at a capture circuit 130.

Multiplexor 116 is controlled by a select signal SEL on line 156. Basedon the signal relationship between the XCLK and DQ signals, the SELsignal enables MUX 116 to select either the CLKIN or CLK90 and passes itto node 158 of master DLL 112. If the XCLK and DQ signals are centeraligned, the CLKIN signal is passed to master DLL 112. If the XCLK andDQ signals are edge aligned, the CLK90 signal is passed to master DLL112. The signal at node 158 of master DLL 112 is referred to as CLKDLLsignal.

Master DLL 112 includes a delay line 160 connected to node 158. Delayline 160 connects to a controller 162 via a plurality of control bits164. Delay line 160 provides a delayed signal DLLout at node 166, whichconnects to a clock tree circuit 170. Clock tree circuit 170 generatescapture clock signal CAPCLK at node 118. Clock tree circuit 170 alsoprovides a feedback signal CLKFB to a model circuit 174 via line 172.Model circuit 174 receives the CLKFB signal and provides a masterfeedback signal CLKFBMS on line 178. A phase detector 180 connects tonode 158 and 178 to receive the CLKDLL (CLKIN or CLK90) and the CLKFBMSsignal. Phase detector 180 connects to controller 162 via a plurality oflines 182. From the arrangement of master DLL 122, clock receiver 103,MUX 116, delay line 160 and clock tree circuit 170 form a forward path113; model circuit 174 is the feedback path 115, which is locatedbetween clock tree circuit 170 and phase detector 180.

Circuit elements of master DLL 112, such as delay line 160, clock treecircuit 170, phase detector 180, controller 162, and model circuit 174are conventional circuit elements included in a delay locked loop. SlaveDLL 114 can be any type of conventional delay locked loop, which cangenerate a clock signal with 90 degrees out of phase to the referencesignal. Therefore, the constructions of these circuit elements of masterDLL and slave DLL 112 and 114 will not be described in detailed in thisdisclosure.

In general, delay line 160 includes a plurality of delay cells connectedin series, in which each of the delay cells can delay a signal for apredetermined amount of time. Depending on the number of delay cellsselected, the amount of delay applied to the CLKDLL signal variesaccordingly.

Phase detector 180 is used to detect a difference between the edges oftwo signals and provides shifting signals. The shifting signals includeshift right and shift left signals. In this case, phase detector 180compares the CLKDLL and CLKFBMS signals to provide shifting signals.When the CLKDLL and CLKFBMS signals are synchronized, phase detector 180deactivates or disables the shifting signals.

Controller 162 includes a shift register, which performs shiftingoperations based on the shifting signals received from phase detector180. The shifting operations can be a shift right or a shift leftoperation, which is performed to adjust the amount of delay applied tothe CLKDLL signal at node 158. When shifting to the right, controllerselects less delay cells in delay line 160 to decrease the amount ofdelay applied to the CLKDLL (CLKIN or CLK90) signal. In the opposite,when shifting to the left, controller selects more delay cells in delayline 160 to increase the amount of delay applied to the CLKDLL signal.By adjusting the delay amount applied to the CLKDLL signal, the CLKFBMSsignal is adjusted accordingly. When the CLKDLL and CLKFBMS signals aresynchronized, phase detector 180 disables the shifting signals. Thiscauses controller 162 to stop performing the shifting and master DLL 112is locked.

Model circuit 174 in the feedback path 115 includes a dummy MUX 175 anda clock receiver model 176, which is identical to the clock receiver103. Dummy delay 175 is identical to MUX 116. Model circuit 174 is usedto compensate the delay variations of the clock receiver 103 and MUX116. Since clock receiver model 176 of model circuit 174 is identical toclock receiver 103, a delay of clock receiver model 176 is the same as adelay of clock receiver 103.

Clock tree circuit 170 can be a driver and receiver capable of receivinga signal and distributing or producing a plurality of output signalshaving the same signal characteristics. In FIG. 2, clock tree circuit170 provides a plurality or multiple of capture clock signals such asthe CAPCLK signal shown at node 118. For simplicity, only one CAPCLKsignal is shown in FIG. 2. Since clock tree circuit 170 provides amultiple of capture clock signals, a multiple of data signals such asDin signal can be captured by other capture circuits such as capturecircuit 130 using the multiple capture clock signals distributed byclock tree 170.

From the arrangement of capture clock generator 100 of FIG. 2, delayvariations between clock receiver 103 and data receiver 122 are properlycompensated because of the inclusion of model circuit 174 in feedbackpath 115 and data receiver model 105 in the forward path 113. Inaddition, since clock tree circuit 170 is included in the forward pathof master DLL 112, delay variation of clock tree circuit 170 is alsocompensated. Thus, when both master DLL 112 and slave DLL 114 arelocked, the CAPCLK signal is center aligned with the internal datasignal Din.

The operation of clock generator 100 is described below with the timingdiagram of FIG. 3. The signals shown in FIG. 3 represent the signals attheir respective nodes or lines shown in FIG. 2. In operation, receivingcircuit 102 receives XCLK signal at input 104 and output the CLKINsignal on node 106. Data receiver 122 receives the DQ signal at node 124and provides the Din signal at node 126. Receiving circuit 102 has apropagation delay of T_(RX1)+T_(RX2). T_(RX1) is a delay of clockreceiver 103; T_(RX2) is a delay of data receiver model 105. Datareceiver 122 has a delay of T_(RX2), which is the same as data receivermodel 105. In FIG. 3, the CLKIN signal follows the XCLK signal after adelay indicated by T_(RX1)+T_(RX2). The Din signal follows the DQ signalafter a delay indicated by T_(RX2). For illustrating the invention, itis assumed that the XCLK and DQ signals are edge aligned.

Slave DLL 114 receives the CLKIN signal and produces the CLK90 signal.In FIG. 3, the CLK90 signal is 90 degrees (or ¼ clock cycle T_(CLK)delay) out of phase with the CLKIN signal. Since the XCLK and DQ signalsare assumed to be edge aligned, the SEL signal enables MUX to pass theCLK90 to master DLL 112.

At DLL 112, the CLKDLL signal is a delayed version of the CLK90 signal.The delay is caused by MUX 116. FIG. 3 shows that the CLKDLL signalfollows the CLK90 signal after a T_(MUX) delay; T_(MUX) is a delay ofMUX 116. After receiving the CLKDLL signal, delay line 160 applies anamount of delay to the CLKDLL signal and generates the DLLout signal onnode 166. Thus, the DLLout signal is a delayed version of the CLKDLLsignal. Clock tree circuit 170 receives the DLLout signal and generatesthe CAPCLK signal on node 118. The same version of the CAPCLK signal isalso provided as the CLKFB signal, which is passed to the model circuit174 of feedback path 115.

The output of the model circuit 174, the CLKFBMS signal, is fed backinto the phase detector 180. Phase detector 180 compares the relativetiming between the edges of the CLKDLL and CLKFBMS signals to provideshifting signals to controller 162 via lines 182. Controller 62, basedon the shifting signals, adjusts the amount of delay applied to theCLKDLL signal until the CLKDLL and CLKFBMS signals are synchronized.When the CLKDLL and CLKFBMS signals are synchronized, phase detector 162disables the shifting signals. This causes controller 162 to stopperforming the shifting operations and master DLL 112 is locked.

In FIG. 3, when master DLL 112 is locked, the CLKDLL and CLKFBMS signalsare synchronized. The CLKFBMS signal follows the CLKFB signal (orCAPCLK) after a delay T_(RX1)+T_(MUX) caused by model circuit 174.T_(MUX) is the delay of dummy MUX 175 which is the same as the delay ofMUX 116. Since data receiver 122 has a delay of T_(RX2), the Din signalis shown following the DQ signal after a delay indicated by T_(RX2).

When both master DLL 112 and slave DLL 114 are locked, the CAPCLK signalprovided by master DLL 112 is used to capture the Din signal at capturecircuit 130. Since the timing relationship between the XCLK and DQsignals are properly adjusted by clock generator 100, the CAPCLK iscenter aligned with the Din signal.

FIG. 4 is a diagram showing details of timing delays of the clockgenerator 100 of FIG. 2. For clarity and simplicity, reference numbersof the elements of clock generator 100 are not included in FIG. 4. Atime label in FIG. 4 indicates the delay time of the circuit elementlocated next to the label. For example, T_(RX1) indicates a delay timeof the clock receiver C Rx, and T_(RX2) indicates a delay time of thedata receiver D Rx.

The following equations show timing relationships of the signals ofclock generator 100 shown in FIG. 2.

-   a) CLK90=CLKIN+(¼)T_(CLK) (when slave DLL is locked)-   b) XCLK=DQ (edge aligned)-   c) CLKIN=XCLK+T_(RX1)+T_(RX2)-   d) Din=DQ+T_(RX2)-   e) CAPCLK=CLKIN+T_(MUX)+T_(DLL)+T_(TREE)-   f) CLKFBMS=CAPCLK+T_(RX1)+T_(MUX) (passing the model circuit)-   g) CLKDLL=CLKIN+(¼)T_(CLK)+T_(MUX)-   h) CLKFBMS=CLKDLL+nT_(CLK) (when master DLL is locked)    $\begin{matrix}    {\begin{matrix}    {{{CAPCLK} + T_{RX1} + T_{MUX}} = {{CLKIN} + {\left( {1/4} \right)T_{CLK}} + T_{MUX} +}} \\    {{nT}_{CLK}} \\    {= {{XCLK} + T_{RX1} + T_{RX2} +}} \\    {{\left( {1/4} \right)T_{CLK}} + T_{MUX} + {nT}_{CLK}}    \end{matrix}{{CAPCLK} = {{XCLK} + T_{RX2} + {\left( {1/4} \right)T_{CLK}} + {nT}_{CLK}}}{{CAPCLK} = {{DQ} + T_{RX2} + {\left( {1/4} \right)T_{CLK}} + {nT}_{CLK}}}{{CAPCLK} = {{Din} + {\left( {1/4} \right)T_{CLK}} + {nT}_{CLK}}}} & \left. g \right)    \end{matrix}$

From equation g), the CAPCLK signal is equal to the internal data signalDin plus a quarter of a clock cycle; T_(CLK) is the cycle time (period)of the XCLK signal. The nT_(CLK) in equations h) and g)—where n is aninteger—indicates that when the master DLL is locked, the CLKFBMS signalis at least one clock cycle behind the CLKDLL signal. If the delay timeof the master DLL 112 is smaller than the clock period of the XCLK, thenn is 1. If the delay time of the master DLL 112 is greater than oneT_(CLK), then n is two or more. In any case, any integer value of n willnot affect the timing relationship between the CAPCLK and Din signals.In other words, the timing relationship between the CAPCLK and Dinsignals is independent of the frequency of the XCLK signal. In summary,equation g) demonstrates that the CAPCLK signal of clock generator 100is always a quarter of clock cycle delayed from the Din signal. In otherterms the CAPCLK signal is always center aligned with the Din signal.

FIG. 5 is a block diagram of slave DLL 114 according to one embodimentof the invention. Slave DLL 114 includes a first delay line 140connected to a second delay line 142 via line or node 144. Delay line140 receives the CLKIN signal and generates the slave output clocksignal CLK90 at node 144. Delay line 142 receives the CLK90 signal atnode 144 and generates the CLKFBSL signal at node 152. Delay lines 140and 142 connect to controller 146 via a plurality of control bits 141.Controller 146 connects to a phase detector 148 via a plurality of lines149. Phase detector 148 receives the CLKIN* and CLKFBSL signals at nodes150 and 152. The CLKIN* signal is an inverse of the CLKIN signal.

In operation, delay line 140 applies an amount of delay to the CLKINsignal to produce the CLK90 signal at node 144. Delay line 142 appliesthe same amount of delay to the CLK90 signal to generate the CLKFBSLsignal. Phase detector 148 compares the CLKIN* and CLKFBSL signals toproduce shifting signals via lines 149 to controller 146. Controller 146adjusts the amount of delay applied to the CLKIN and CLK90, based on theshifting signals, until the CLKIN* and CLKFBSL signals are synchronized.When the CLKIN* and CLKFBSL signals are synchronized, phase detector 148disables the shifting signals on lines 149. This causes controller 146to stop adjusting the amount of delay and slave DLL 114 is locked. Whenslave DLL 114 is locked, the CLK90 signal is one-fourth cycle delayedfrom the CLKIN signal, the CLKFBSL signal is one-half cycle delayed fromthe CLKIN signal. In other words, when slave DLL 114 is locked, theCLK90 signal is 90 degrees out of phase with the CLKIN signal, and theCLKFBSL signal is 180 degrees out of phase with the CLKIN signal.

FIG. 6 is a timing diagram of the slave DLL 144 when it is locked. Inthe Figure, the CLKIN* signal is an inverse of the CLKIN signal. TheCLKIN* and CLKFBSL signals are synchronized. The CLK90 is one-fourthclock cycle delayed from the CLKIN signal as indicated by (¼) T_(CLK).

The purpose of slave DLL 114 of FIG. 5 is to receive an input clocksignal, such as the CLKIN signal, and to produce an output clock signal,which is 90 degrees out of phase with the input signal. Thus, any typeof DLL, either analog or digital, can be used to achieve the samepurpose as slave DLL 114. Therefore, slave DLL 114 can be substituted bya DLL having a different construction from slave DLL 114 shown in FIG.5.

FIG. 7 is a block diagram of a clock generator 700 according to anotherembodiment of the invention. Clock generator 700 is similar to clockgenerator 100 of FIG. 2. However, clock generator 700 is used foranother application according to the embodiment of the invention. Inembodiment of FIG. 2, clock generator 100 generates a capture clocksignal (CAPCLK) to capture an internal data signal (Din); the CAPCLKsignal is center aligned with the Din signal. In the embodiment of FIG.7, Clock generator 700 generates an output data signal OUTPUT DATA; theOUTPUT DATA signal is center aligned with the external clock signalXCLK.

In clock generator 700, the forward path 113 does not include a datareceiver model. However, additional data path circuit 720 is included.Data path circuit 720 receives an internal data signal, indicated asINTERNAL DATA, and provides the OUTPUT DATA signal. In the embodiment ofclock generator 700, the delay variations of the XCLK and OUTPUT DATAsignals are compensated by a model circuit 730. Model circuit 730includes models of MUX 116, clock receiver 103, and data path circuit720.

Clock generator 700 operates in a similar fashion as clock generator 100of FIG. 2. Slave DLL 114 receives the CLKIN signal and generates theCLK90 signal, which is 90 degrees out of phase with the CLKIN signal.MUX 116 passes the CLK90 signal to master DLL 112. Master DLL 112receives the CLK90 signal and produces the CAPCLK signal. Data pathcircuit 720 receives the INTERNAL DATA and CAPCLK signals to generatethe OUTPUT DATA signal. Because data path circuit 720 and clock receiver103 are modeled in model circuit 730, when master DLL 112 is locked, theOUTPUT DATA signal is 90 degrees out of phase with the external clocksignal XCLK. In summary, clock generator 700 uses slave DLL 114 andmaster DLL 112 to generate the output data signal OUTPUT DATA, which iscenter aligned with the XCLK signal.

FIG. 8 is a block diagram of a memory system 800 according to oneembodiment the invention. Memory system includes a memory device 800 anda memory controller 801. Memory device 800 includes a plurality ofmemory cells 802 generally arranged in rows and columns. Row decodecircuit 804 and column decode circuit 806 access the rows and columns inresponse to an address, provided on a plurality of address lines 808.Data communication to and from memory device 800 are transmitted viainput/output circuit 818 in response to command signals on control lines814. Both memory device 800 and memory controller 801 receive anexternal clock signal XCLK on line 825. Memory controller 801 includes aclock generator 830. Clock generator 830 represents clock generator 100or 700 according to the invention. Data is transferred between memorycontroller 801 and memory device 800 through data lines 810.

In a memory operation such as read operation, an external data signalread from memory cells 802 is sent to memory controller through lines810. Clock generator 830 produces a capture clock signal, based on theXCLK signal, to capture an internal data signal, which is a delayedversion of the data signal sent from memory cells 802. The capture clocksignal is center aligned with the internal data signal. The externaldata signal, the internal data signal, and the capture clock signaldescribed in this Figure are represented by the DQ, Din and CAPCLKsignals in FIG. 2. In summary, clock generator 830 of memory controller801 generates a capture clock signal to capture an internal data signalDin provided by memory device 800. The capture clock signal CAPCLK iscenter aligned with the internal data signal Din.

In another memory operation such as a write operation, data from memorycontroller 801 is written into memory cells 802 via lines 810 inresponse to address and control signals on lines 808 and 814. Thesignals provided on control, address and data lines 814, 808 and 810 areprovided by clock generator 830. In this case, clock generator 830represents clock generator 700 of FIG. 7. The signals provided oncontrol, address and data lines 814, 808 and 810 are the signalrepresented by the OUTPUT DATA signal of data path circuit 720 of FIG.7. In summary, clock generator 830 of memory controller 801 generatesthe data signal DATA as a control, address or data signal provided tomemory device 800. The data signal DATA is center aligned with theexternal clock signal XCLK.

Memory device 800 of FIG. 8 can be a dynamic random access memory (DRAM)or other types of memory circuits such as SRAM (Static Random AccessMemory) or Flash memories. Furthermore, the DRAM could be a synchronousDRAM commonly referred to as SGRAM (Synchronous Graphics Random AccessMemory), SDRAM (Synchronous Dynamic Random Access Memory), SDRAM II, orDDR SDRAM (Double Data Rate SDRAM), as well as Synchlink or RambusDRAMs. Those of ordinary skill in the art will readily recognize thatmemory device 800 of FIG. 8 is simplified to illustrate one embodimentof a memory device of the present invention and is not intended to be adetailed description of all of the features of a memory device.

FIG. 9 shows a processing system 900 according to the invention. System900 includes processor 902 connected to a memory device 904. System 900can also include many other devices such as, input/output devices, andothers. These other devices are omitted from FIG. 9 for ease ofillustration. Processor 902 can be a microprocessor, digital signalprocessor, embedded processor, microcontroller, or the like. In theembodiment of FIG. 9, processor 902 includes a memory controller 901However, in other embodiments such as in the embodiment of FIG. 8,memory controller 930 is an independent device separated from processor902. Processor 902 and memory device 904 communicate using addresssignals on lines 908, control signals on lines 910, and data signals onlines 906. Both processor 902 and memory device 904 receive an externalclock signal XCLK on line 925.

Memory controller 901 includes clock generator 930. Clock generator 930represents clock generator 100, 700 or 830 according to the invention asdescribed and shown in FIG. 2, 7 or 8. According to the invention, clockgenerator 930 of memory controller 901 generates a capture clock signalto capture a data signal from memory device 904. The capture clocksignal is center aligned with the data signal. According to theinvention, clock generator 930 of memory controller 901 also generates adata signal as a control, address, or data signal provided to memorydevice 904. The data signal is center aligned with the external clocksignal.

CONCLUSION

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement which is calculated to achieve the same purpose maybe substituted For the specific embodiment shown. This application isintended to cover any adaptations or variations of the presentinvention. Therefore, it is intended that this invention be limited onlyby the claims and the equivalents thereof.

1. A memory device comprising: a data receiver for receiving an inputdata signal to provide an internal data signal; a receiving circuitincluding an input node for receiving an input clock signal, and anoutput node for providing an internal clock signal; a slave delay lockedloop (DLL) for receiving the internal clock signal to generate a slavesignal; a selector for selecting between the slave signal and theinternal clock signal to provide a DLL input signal; and a master DLLresponsive to the DLL input signal for generating a capture signal tocapture the internal signal.
 2. The memory device of claim 1, whereinthe receiving circuit includes a first receiver, and a second receivercoupled in series with the first receiver between the input and outputnodes.
 3. The memory device of claim 2, wherein the second receiverincludes a circuit model of the data receiver.
 4. The memory device ofclaim 3, wherein the master DLL includes: a forward path for providingthe capture signal; a feedback path for delaying a copy of the capturesignal to provide a feedback signal; and a control circuit for adjustinga timing of the capture signal based on a timing relationship betweenthe feedback signal and the DLL input signal.
 5. The memory device ofclaim 4, wherein the feedback path includes a model circuit having afirst circuit unit and a second circuit unit coupled in series with thefirst circuit unit for delaying the copy of the feedback signal, whereinthe first circuit unit includes a circuit model of the second receiverof the receiving circuit, and wherein the second circuit unit includes acircuit model of the selector.
 6. The memory device of claim 1, whereinthe slave DLL is configured to generate the slave signal having a 90degrees out of phase with the internal clock signal.
 7. The memorydevice of claim 1, wherein the master DLL is configured to generate thecapture signal having a 90 degrees out of phase with the internal datasignal.
 8. The memory device of claim 1, wherein the selector isconfigured to select the slave signal to be the DLL input signal whenthe input clock signal is edge aligned with the input data signal, andwherein the selector is configured to select the internal clock signalto be the DLL input signal when the input clock signal is center alignedwith the input data signal.
 9. A memory device comprising: a datareceiver for receiving an input data signal to provide an internal datasignal; a receiving circuit including an input node for receiving aninput clock signal, and an output node for providing an internal clocksignal, the receiving circuit also including a first receiver, and asecond receiver coupled in series with the first receiver between theinput and output nodes, wherein the second receiver includes a circuitmodel of the data receiver; a slave delay locked loop (DLL) forreceiving the internal clock signal to generate a slave signal; and amaster DLL responsive to the slave signal for generating a capturesignal to capture the internal signal.
 10. The memory device of claim 9,wherein the master DLL is configured to generate the capture signalhaving a 90 degrees out of phase with the internal data signal.
 11. Thememory device of claim 9, wherein the master DLL is configured togenerate the capture signal having a 90 degrees out of phase with theinternal data signal when the input clock signal is edge aligned withthe input data signal.
 12. The memory device of claim 9, wherein themaster DLL includes: a forward path for providing the capture signal; afeedback path for delaying a copy of the capture signal to provide afeedback signal; and a control circuit for adjusting a timing of thecapture signal based on the feedback signal.
 13. The memory device ofclaim 12, wherein the feedback path includes a model circuit having afirst circuit unit and a second circuit unit coupled in series with thefirst circuit unit for delaying the copy of the feedback signal, whereinthe first circuit unit includes a circuit model of the data receiver.14. A memory device comprising: a receiving circuit having a receiverfor receiving an input clock signal to produce an internal clock signal;a slave delay locked loop (DLL) for receiving the internal clock signalto produce a slave signal; a selector for selecting between the internalclock signal and the slave signal to provide a DLL input signal; amaster DLL responsive to the DLL input signal for generating a capturesignal to capture an internal data signal; and a data path circuitresponse to the capture signal to provide an output data signal based onthe internal data signal.
 15. The memory device of claim 14, wherein theselector is configured to select the internal clock signal to be the DLLinput signal when the input clock signal is center aligned with theinput data signal, and wherein the selector is configured to select theslave signal to be the DLL input signal when the input clock signal isedge aligned with the input data signal.
 16. The memory device of claim14, wherein the master DLL includes: a forward path for providing thecapture signal; a feedback path for delaying a copy of the capturesignal to provide a feedback signal; and a control circuit for adjustinga timing of the capture signal based on a timing relationship betweenthe feedback signal and the DLL input signal.
 17. The memory device ofclaim 16, wherein the feedback path includes model circuit having aseries combination of a first circuit unit, a second circuit unit, and athird circuit unit for delaying the copy of the feedback signal, whereinthe first circuit unit includes a circuit model of the receiver of thereceiving circuit, wherein the second circuit unit includes a circuitmodel of the selector, and wherein the third circuit unit includes acircuit model of the data path circuit.
 18. A memory system comprising:a plurality of memory cells; and a controller coupled to the memorycells, the controller including: a receiving circuit having an inputnode for receiving an input clock signal, and an output node forproducing an internal clock signal, the receiving circuit including afirst receiver, and a second receiver coupled in series with the firstreceiver between the input and output nodes; a data receiver forreceiving an input data signal from the memory cells to produce aninternal data signal, wherein the second receiver of the receivingcircuit includes a circuit model of the data receiver; a slave delaylocked loop (DLL) for receiving the internal clock signal to produce aslave signal having a 90 degrees out of phase with the internal clocksignal; and a master DLL responsive to the slave signal to generate acapture signal to capture the internal data signal.
 19. The memorysystem of claim 18, wherein the master DLL includes: a forward path forproviding the capture signal; a feedback path for delaying a copy of thecapture signal to provide a feedback signal; and a control circuit foradjusting a timing of capture signal based on a timing relationshipbetween the feedback signal and the DLL input signal.
 20. The memorysystem of claim 19, wherein the feedback path includes model circuithaving a first circuit unit and a second circuit unit coupled in serieswith the first circuit unit for delaying the copy of the feedbacksignal, and wherein the first circuit unit includes a circuit model ofthe second receiver of the receiving circuit.
 21. The memory system ofclaim 18, wherein the input data signal includes a data signalrepresenting data stored in the memory cells.
 22. The memory system ofclaim 18, wherein the master DLL is configured to generate the capturesignal having a 90 degrees out of phase with the internal data signal.23. A memory system comprising: a plurality of memory cells; and acontroller coupled to the memory cells, the controller including: areceiving circuit including an input node for receiving an input clocksignal, and an output node for providing an internal clock signal; adata receiver for receiving an input data signal to provide an internaldata signal, a slave delay locked loop (DLL) for receiving the internalclock signal to generate a slave signal; a multiplexer coupled to thereceiving circuit and the slave DLL for providing a DLL input signal,wherein the multiplexer is configured to select the internal clocksignal to be the DLL input signal when the input clock signal is centeraligned with the input data signal, and wherein the multiplexer isconfigured to select the slave signal to be the DLL input signal whenthe input clock signal is edge aligned with the input data signal; and amaster DLL responsive to the DLL input signal for generating a capturesignal to capture the internal signal.
 24. The memory system of claim23, wherein the receiving circuit includes a first receiver, and asecond receiver coupled in series with the first receiver between theinput and output nodes.
 25. The memory system of claim 24, wherein thesecond receiver includes a circuit model of the data receiver.
 26. Thememory system of claim 25, wherein the slave DLL is configured togenerate the slave signal having a 90 degrees out of phase with theinternal clock signal.
 27. The memory device of claim 23, wherein themaster DLL includes: a forward path for providing the capture signal; afeedback path for delaying a copy of the capture signal to provide afeedback signal; and a control circuit for adjusting a timing of thecapture signal based on a timing relationship between the feedbacksignal and the DLL input signal.
 28. The memory system of claim 27,wherein the feedback path includes a model circuit having a firstcircuit unit and a second circuit unit coupled in series with the firstcircuit unit for delaying the copy of the feedback signal, wherein thefirst circuit unit includes a circuit model of the second receiver ofthe receiving circuit, and wherein the second circuit unit includes acircuit model of the multiplexer.
 29. A system comprising: a processor;a memory device coupled to the processor, the memory device including aplurality of memory cells to store data; and a memory controller coupledto the memory device, the memory controller including: a data receiverfor receiving an input data signal to provide an internal data signal, areceiving circuit including an input node for receiving an input clocksignal, and an output node for providing an internal clock signal; aslave delay locked loop (DLL) for receiving the internal clock signal togenerate a slave signal; a multiplexer for selecting between the slavesignal and the internal clock signal to provide a DLL input signal; anda master DLL responsive to the DLL input signal for generating a capturesignal to capture the internal signal.
 30. The system of claim 29,wherein the receiving circuit includes a first receiver, and a secondreceiver coupled in series with the first receiver between the input andoutput nodes.
 31. The system of claim 30, wherein the second receiverincludes a circuit model of the data receiver.
 32. The system of claim29, wherein the slave DLL is configured to generate the slave signalhaving a 90 degrees out of phase with the internal clock signal.
 33. Thesystem of claim 29, wherein the master DLL is configured to generate thecapture signal having a 90 degrees out of phase with the internal datasignal.
 34. The system of claim 29, wherein the multiplexer isconfigured to select the slave signal to be the DLL input signal whenthe input clock signal is edge aligned with the input data signal, andwherein the multiplexer is configured to select the internal clocksignal to be the DLL input signal when the input clock signal is centeraligned with the input data signal.
 35. A method comprising: propagatingan input data signal through a data receiver to provide an internal datasignal; propagating an input clock signal through a series combinationof a first receiver and a second receiver to provide an internal clocksignal, wherein the second receiver includes a circuit model of the datareceiver; generating a slave signal based on the internal clock signal;and generating a capture signal based on the slave signal to capture theinternal data signal.
 36. The method of claim 35, wherein the slavesignal is 90 degrees out of phase with the internal clock signal. 37.The method of claim 36, wherein the capture signal is 90 degrees out ofphase with the internal data signal.
 38. The method of claim 35, whereinthe generating the capture signal includes: propagating the slave signalon a forward path; delaying copy of capture signal to generate afeedback signal on a feedback path; and adjusting a delay applied to theforward path based on a signal relationship between the slave signal andthe feedback signal.
 39. The method of claim 38, wherein the delayingthe copy of the capture signal includes propagating the copy of thecapture signal through a circuit unit of the feedback path, wherein thecircuit unit includes a circuit model of the receiver of the receivingcircuit.
 40. A method comprising: propagating an input data signalthrough a data receiver to provide an internal data signal; propagatingan input clock signal through a receiving circuit to provide an internalclock signal; generating a slave signal based on the internal clocksignal; selecting between the internal clock signal and the slave signalto provide a delay locked loop (DLL) input signal, wherein the selectingis based on a timing relationship between the input data signal and theinput clock signal; and generating a capture signal based on the DLLinput signal.
 41. The method of claim 40, wherein propagating the inputclock signal includes propagating the input clock through a seriescombination of a first receiver and a second receiver of the receivingcircuit.
 42. The method of claim 41, wherein the second receiver of thereceiving circuit is a circuit model of the data receiver.
 43. Themethod of claim 42, wherein the DLL input signal is 90 degrees out ofphase with the internal clock signal.
 44. The method of claim 43,wherein the capture signal is 90 degrees out of phase with the internaldata signal.
 45. The method of claim 40, wherein the internal clocksignal is selected to provide the DLL input signal when the input clocksignal is center aligned with the input data signal, and wherein theslave signal is selected to provide the DLL input signal when the inputclock signal is edge aligned with the input data signal.
 46. The methodof claim 40, wherein the generating the capture signal includes:propagating the DLL input signal on a forward path; delaying copy ofcapture signal to generate a feedback signal on a feedback path; andadjusting a delay applied to the forward path based on a signalrelationship between the DLL input signal and the feedback signal. 47.The method of claim 46, wherein the delaying the copy of the capturesignal includes propagating the copy of the capture signal through acircuit unit of the feedback path, wherein the circuit unit includes acircuit model of the data receiver.